1. Field of the Invention
The present invention relates to a device for and method of simulation and, more particularly, to a device for and method of simulating an electrostatic discharge (ESD) to a semiconductor integrated circuit.
2. Description of the Background Art
An ESD applied to a semiconductor integrated circuit can impair the function of the integrated circuit or destroy the integrated circuit itself. Thus, a highly ESD-resistant device structure or circuit configuration is desired. However, it becomes more difficult to hold desired ESD resistance as semiconductor devices are reduced in size.
An ESD test which is carried out on packaged final products leads to a tendency toward an increase in time period between modifying a device structure or circuit configuration and obtaining a test result, and hence becomes a significant factor that determines a product development period. Therefore, it has been desired to use simulation to predict a modification in highly ESD-resistant device structure or circuit configuration with high precision.
With an ESD applied to a semiconductor device, the semiconductor device receives high voltage to reveal a pronounced shape effect which would present no problem at normal operating voltage. For example, if the gate widths of MOSFETs are not uniform but differ according to the position because of the manufacturing process, current is liable to concentrate on a position where the gate width is smaller to cause device breakdown. An ESD simulation which takes such a device shape effect into consideration has required the use of a three-dimensional device simulation. The device simulation uses a computer to determine device characteristics from the behavior of carriers in the device, based on the physical shape and impurity distribution of the device.
However, the device simulation which divides a semiconductor device structure to be analyzed into small regions called meshes and calculates the potential and carrier concentration at a node which represents each of the meshes is required to perform calculations at as numerous as not less than hundreds of thousands of nodes. Therefore, the method using the three-dimensional device simulation is disadvantageous in requiring too much time for calculations.
According to a first aspect of the present invention, a simulation device comprises: to-be-analyzed block dividing means receiving a netlist defining a circuit to be simulated and for dividing a predetermined to-be-analyzed block specifying a device included in the circuit to be simulated into a plurality of to-be-analyzed sub-blocks arranged in a predetermined direction, with equivalence with the predetermined to-be-analyzed block maintained, to output a modified netlist defining a new circuit to be simulated in which the predetermined to-be-analyzed block is replaced with the plurality of to-be-analyzed sub-blocks; and circuit simulation means for performing a circuit simulation on the new circuit to be simulated which is defined by the modified netlist, wherein the to-be-analyzed block dividing means is capable of individually setting circuit simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-blocks.
Preferably, according to a second aspect of the present invention, the simulation device of the first aspect further comprises parameter input means for inputting an input parameter to the to-be-analyzed block dividing means, the input parameter containing information which determines the circuit simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-blocks, wherein the to-be-analyzed block dividing means individually sets the circuit simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-blocks, based on the input parameter.
Preferably, according to a third aspect of the present invention, in the simulation device of the first or second aspect, the predetermined to-be-analyzed block includes a MOS transistor which takes a resistance element into consideration, and the predetermined direction includes the direction of the gate width of the MOS transistor.
Preferably, according to a fourth aspect of the present invention, in the simulation device of the third aspect, the to-be-analyzed block dividing means establishes an electric connection between adjacent ones of the plurality of to-be-analyzed sub-blocks through a connecting resistor.
According to a fifth aspect of the present invention, a simulation device comprises: to-be-analyzed region dividing means receiving computational structure data defining a circuit structure to be simulated which is simulatable in a three-dimensional device simulation and for dividing a predetermined to-be-analyzed region having a three-dimensional structure and specifying a device included in the circuit structure to be simulated into a plurality of to-be-analyzed sub-regions arranged in a predetermined direction and each simulatable in a two-dimensional device simulation, with equivalence with the predetermined to-be-analyzed region maintained, to output modified computational structure data defining a new circuit structure to be simulated in which the predetermined to-be-analyzed region is replaced with the plurality of to-be-analyzed sub-regions; and device simulation means for performing a two-dimensional device simulation on the new circuit structure to be simulated which is defined by the modified computational structure data.
Preferably, according to a sixth aspect of the present invention, the simulation device of the fifth aspect further comprises parameter input means for inputting an input parameter to the to-be-analyzed region dividing means, the input parameter containing information which determines device simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-regions, wherein the to-be-analyzed region dividing means individually sets the device simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-regions, based on the input parameter.
Preferably, according to a seventh aspect of the present invention, in the simulation device of the fifth or sixth aspect, the predetermined to-be-analyzed region includes a MOS transistor which takes a resistance element into consideration, and the predetermined direction includes the direction of the gate width of the MOS transistor.
Preferably, according to an eighth aspect of the present invention, in the simulation device of the seventh aspect, the to-be-analyzed region dividing means establishes an electric connection between adjacent ones of the plurality of to-be-analyzed sub-regions through a connecting resistor.
According to a ninth aspect of the present invention, a method of simulation comprises the steps of: (a) reading a netlist defining a circuit to be simulated; (b) selecting a predetermined to-be-analyzed block to be divided which specifies a device out of the circuit to be simulated; (c) dividing the predetermined to-be-analyzed block into a plurality of to-be-analyzed sub-blocks arranged in a predetermined direction and individually setting circuit simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-blocks; (d) establishing an electric connection between the plurality of to-be-analyzed sub-blocks so as to maintain equivalence with the predetermined to-be-analyzed block, and thereafter outputting a modified netlist defining a new circuit to be simulated in which the predetermined to-be-analyzed block is replaced with the plurality of to-be-analyzed sub-blocks; and (e) performing a circuit simulation on the new circuit to be simulated which is defined by the modified netlist.
According to a tenth aspect of the present invention, a method of simulation comprises the steps of: (a) reading computational structure data defining a circuit structure to be simulated which is simulatable in a three-dimensional device simulation; (b) selecting a predetermined to-be-analyzed region to be divided, the predetermined to-be-analyzed region having a three-dimensional structure and specifying a device included in the circuit structure to be simulated; (c) dividing the predetermined to-be-analyzed region into a plurality of to-be-analyzed sub-regions arranged in a predetermined direction and each simulatable in a two-dimensional device simulation; (d) establishing an electric connection between the plurality of to-be-analyzed sub-regions so as to maintain equivalence with the predetermined to-be-analyzed region, and thereafter outputting modified computational structure data defining a new circuit structure to be simulated in which the predetermined to-be-analyzed region is replaced with the plurality of to-be-analyzed sub-regions; and (e) performing a two-dimensional device simulation on the new circuit structure to be simulated which is defined by the modified computational structure data.
According to an eleventh aspect of the present invention, a method of setting a process condition using the method of simulation according to the ninth aspect comprises the steps of: (a) performing a method of simulation as recited in the ninth aspect using as the circuit to be simulated a predetermined semiconductor integrated circuit manufactured through a manufacturing process with a temporary manufacturing process condition established therein; (b) judging whether or not the circuit to be simulated satisfies a predetermined standard, based on a result of the simulation performed in the step (a); (c) modifying the temporary manufacturing process condition to execute the steps (a) and (b) again when it is judged in the step (b) that the circuit to be simulated does not satisfy the predetermined standard; and (d) setting an actual manufacturing process condition for use in actual manufacture of the predetermined semiconductor integrated circuit by substituting the temporary manufacturing process condition for the actual manufacturing process condition when it is judged in the step (b) that the circuit to be simulated satisfies the predetermined standard.
According to a twelfth aspect of the present invention, a method of setting a process condition using the method of simulation according to the tenth aspect comprises the steps of: (a) performing a method of simulation as recited in the tenth aspect using as the circuit structure to be simulated a predetermined semiconductor integrated circuit manufactured through a manufacturing process with a temporary manufacturing process condition established therein; (b) judging whether or not the circuit structure to be simulated satisfies a predetermined standard, based on a result of the simulation performed in the step (a); (c) modifying the temporary manufacturing process condition to execute the steps (a) and (b) again when it is judged in the step (b) that the circuit structure to be simulated does not satisfy the predetermined standard; and (d) setting an actual manufacturing process condition for use in actual manufacture of the predetermined semiconductor integrated circuit by substituting the temporary manufacturing process condition for the actual manufacturing process condition when it is judged in the step (b) that the circuit structure to be simulated satisfies the predetermined standard.
A thirteenth aspect of the present invention is intended for a computer readable recording medium on the method of simulation according to the ninth aspect. The recording medium has stored thereon a program for performing a method of simulation as recited in the ninth aspect.
A fourteenth aspect of the present invention is intended for a computer readable recording medium on the method of simulation according to the tenth aspect. The recording medium has stored thereon a program for performing a method of simulation as recited in the tenth aspect.
As described hereinabove, the to-be-analyzed block dividing means of the simulation device according to the first aspect of the present invention divides the predetermined to-be-analyzed block into the plurality of to-be-analyzed sub-blocks arranged in the predetermined direction, with equivalence with the predetermined to-be-analyzed block maintained, to output the modified netlist defining the new circuit to be simulated in which the predetermined to-be-analyzed block is replaced with the plurality of to-be-analyzed sub-blocks. Further, the to-be-analyzed block dividing means is capable of individually setting the circuit simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-blocks.
The circuit simulation may be performed on the circuit to be simulated which shows a change in device shape in the predetermined direction by providing the different circuit simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-blocks. This provides a simulation result that precisely reflects the device shape change in the predetermined direction, which has not been taken into consideration in a circuit simulation of a single to-be-analyzed block, in a short period of calculation time.
The to-be-analyzed block dividing means of the simulation device according to the second aspect of the present invention sets the circuit simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-blocks, based on the input parameter provided from the parameter input means. Therefore, the circuit simulation characteristic values of the respective to-be-analyzed sub-blocks may be externally set at desired values using the parameter input means.
In the simulation device according to the third aspect of the present invention, the predetermined to-be-analyzed block includes the MOS transistor which takes the resistance element into consideration, and the predetermined direction includes the direction of the gate width of the MOS transistor. Therefore, the simulation device can perform the circuit simulation which precisely reflects the device shape change in the direction of the gate width of the MOS transistor.
The to-be-analyzed block dividing means of the simulation device according to the fourth aspect of the present invention establishes the electric connection between adjacent ones of the to-be-analyzed sub-blocks through the connecting resistor, thereby to taken into consideration current flowing in the direction of the gate width as a potential difference across the connecting resistor.
The to-be-analyzed region dividing means of the simulation device according to the fifth aspect of the present invention divides the predetermined to-be-analyzed region into the plurality of to-be-analyzed sub-regions arranged in the predetermined direction and each simulatable in the two-dimensional device simulation, with the equivalence with the predetermined to-be-analyzed region maintained, to output the modified computational structure data defining the new circuit structure to be simulated in which the predetermined to-be-analyzed region is replaced with the plurality of to-be-analyzed sub-regions.
The two-dimensional device simulation which taken into consideration the device shape change in the predetermined direction may be performed by providing the different device simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-regions.
Additionally, the two-dimensional device simulation requires shorter calculation time than the three-dimensional device simulation, to provide the simulation result in a relatively short period of time.
The to-be-analyzed region dividing means of the simulation device according to the sixth aspect of the present invention sets the device simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-regions, based on the input parameter provided from the parameter input means. Therefor e, the device simulation characteristic values of the respective to-be-analyzed sub-regions may be externally set at desired values using the parameter input means.
In the simulation device according to the seventh aspect of the present invention, the predetermined to-be-analyzed region includes the MOS transistor which takes the resistance element into consideration, and the predetermined direction includes the direction of the gate width of the MOS transistor. Therefore, the simulation device can perform the two-dimensional device simulation which precisely reflects the device shape change in the direct ion of the gate width of the MOS transistor.
The to-be-analyzed region dividing means of the simulation device according to the eighth aspect of the present invention establishes the electric connection between adjacent ones of the to-be-analyzed sub-regions through the connecting resistor, thereby to taken into consideration the current flowing in the direction of the gate width as a potential difference across the connecting resistor.
In the step (c) of the method of simulation according to the ninth aspect of the present invention, the predetermined to-be-analyzed block is divided into the plurality of to-be-analyzed sub-blocks arranged in the predetermined direction, and the circuit simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-blocks are individually set. In the step (d), the electric connection is established between the plurality of to-be-analyzed sub-blocks so as to maintain the equivalence with the predetermined to-be-analyzed block, and the modified netlist is outputted which defines the new circuit to be simulated in which the predetermined to-be-analyzed block is replaced with the plurality of to-be-analyzed sub-blocks.
As a result, the circuit simulation may be performed in the step (e) upon the circuit to be simulated which shows a change in device shape in the predetermined direction by providing the different circuit simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-blocks. This provides a simulation result that precisely reflects the device shape change in the predetermined direction, which has not been taken into consideration in a circuit simulation of a single to-be-analyzed block, in a short period of calculation time.
In the step (c) of the method of simulation according to the tenth aspect of the present invention, the predetermined to-be-analyzed region is divided into the plurality of to-be-analyzed sub-regions arranged in the predetermined direction and each simulatable in the two-dimensional device simulation. In the step (d), the electric connection is established between the plurality of to-be-analyzed sub-regions so as to maintain the equivalence with the predetermined to-be-analyzed region, and the modified computational structure data is outputted which defines the new circuit structure to be simulated in which the predetermined to-be-analyzed region is replaced with the plurality of to-be-analyzed sub-regions.
Therefore, the two-dimensional device simulation which precisely reflects the device shape change in the predetermined direction may be performed in the step (e) by providing the different device simulation characteristic values, respectively, of the plurality of to-be-analyzed sub-regions.
Additionally, the two-dimensional device simulation requires shorter calculation time than the three-dimensional device simulation, to provide the simulation result in a relatively short period of time.
In the method of setting a manufacturing process condition according to the eleventh aspect of the present invention, the actual manufacturing process condition is set by substituting the temporary manufacturing process condition for the actual manufacturing process condition when it is judged that the predetermined standard is satisfied, based on the result of the circuit simulation performed according to the simulation method of the ninth aspect. Hence, the actual manufacture of the predetermined semiconductor integrated circuit through the predetermined manufacturing process under the actual manufacturing process condition provides a semiconductor integrated circuit which reliably satisfies the predetermined standard.
In the method of setting a manufacturing process condition according to the twelfth aspect of the present invention, the actual manufacturing process condition is set by substituting the temporary manufacturing process condition for the actual manufacturing process condition when it is judged that the predetermined standard is satisfied, based on the result of the two-dimensional device simulation performed according to the simulation method of the tenth aspect. Hence, the actual manufacture of the predetermined semiconductor integrated circuit through the predetermined manufacturing process under the actual manufacturing process condition provides a semiconductor integrated circuit which reliably satisfies the predetermined standard.
The recording medium according to the thirteenth aspect of the present invention has stored thereon the program for executing the simulation method of the ninth aspect. The execution of the program by the computer provides a simulation result that precisely reflects a device shape change, which has not been taken into consideration in a circuit simulation of a single to-be-analyzed block, in a short period of calculation time.
The recording medium according to the fourteenth aspect of the present invention has stored thereon the program for executing the simulation method of the tenth aspect. The program may be executed by the computer to perform the two-dimensional device simulation that precisely reflects the device shape change.
It is therefore an object of the present invention to provide a device for and method of simulation capable of providing a simulation result which reflects the shape of a device in a short period of calculation time.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.